1. Field of the Invention
This invention relates to computer systems and more particularly to non-volatile memory array controllers employed within computer systems.
2. Description of the Relevant Art
Most computer systems include software code in ROM or flash memory that allows the system to read the operating system software from a disk at power-up. This software code is often referred to as the boot-strap code or boot code, and the process of loading the operating system from the disk is called "booting the system". The boot code typically contains only enough software to read the operating system, which is generally stored on a specific track of the disk. The operating system software itself provides the capability of performing more general read and write accesses. A typical computer system includes a dedicated ROM (read only memory) integrated circuit memory chip referred to as the BIOS (basic input/output system) ROM which contains the boot code and a collection of additional subroutines (referred to as BIOS code) to provide a standard software interface for the system.
Due to the low cost and low power consumption of read only memory, ROM integrated circuits are also becoming a popular storage medium for user software such as word processing programs as well as for the operating system software. This is particularly true for applications within portable computer systems. The read only memory used to store such user software is typically quite large in capacity (compared to that of the BIOS ROM) and is often arranged as one or more ROM banks that may be selectively accessed through a memory controller. The memory capacity or the number of banks comprising this user ROM may typically be varied to suit the needs of a particular user.
FIG. 1 is a block diagram that illustrates the memory organization of a typical computer system 10. The computer system 10 includes a microprocessor central processing unit (CPU) 12 coupled to a RAM controller 14 and a bus bridge 16 through a CPU local bus 18. A random access memory (RAM) unit 20 is coupled to RAM controller 14. Bus bridge 16 provides an interface between CPU local bus 18 and an X-bus 22 and an ISA (Industry Standard Architecture) peripheral bus 24. An 8-bit BIOS ROM unit 26 is coupled to X-bus 22 through a BIOS ROM controller 28, and a 16-bit ROM bulk storage unit 30 is coupled to ISA peripheral bus 24 through a ROM controller 32.
Microprocessor 12 is illustrative of, for example, a model 80486 microprocessor. CPU local bus 18 is a 32-bit bus that supports high speed data transfers between microprocessor 12, RAM controller 14, and bus bridge 16, among other things. The 32-bit RAM unit 20 serves as a primary high speed memory resource for computer system 10.
ROM bulk storage unit 30 is a relatively large storage unit having a capacity of, for example, two Mbytes. BIOS ROM unit 26, on the other hand, is a relatively small memory unit having a capacity of, for example, 128K bytes. Bus bridge 16 controls the transfer of data between CPU local bus 18 and ISA peripheral bus 24, and further controls the transfer of data between CPU local bus 18 and X-bus 22. Bus bridge 16 includes circuitry that converts 8-bit data on X-bus 22 to 32-bit data on CPU local bus 18, and includes similar circuitry that converts 16-bit data on ISA peripheral bus 24 to 32-bit data on CPU local bus 18.
Since the BIOS code is typically shadowed within RAM unit 20 upon system initialization (that is, since the BIOS ROM 26 is transferred into RAM unit 20 upon system initialization and is executed out of the RAM), the use of an 8-bit memory device (rather than a 32-bit or a 16-bit device) for BIOS ROM 26 does not significantly degrade the overall speed characteristics of the system. The use of the 8-bit dedicated memory device for BIOS ROM 26 instead allows for a reduction in the cost of the system when a flash memory device is required, which is relatively expensive in terms of cost-per-bit of storage (compared to standard ROM devices). The bit width of the ROM bulk storage unit 30, on the other hand, can strongly impact the overall performance of the system, and thus it is desirable to maximize the bit width of the ROM bulk storage unit.
Although the memory capacity or the number of banks comprising ROM bulk storage unit 30 can typically be varied according to the user requirements, the separate integrated circuit chip for BIOS ROM 26 is still provided and requires a separate BIOS ROM controller 28. This is true even if a flash memory device is not required to allow reprogramming of the BIOS code. Therefore, overall cost of the system may be relatively high due to the number of integrated circuits incorporated within the system.